Programming MK ports in language C 51. Microcontrollers MCS–51: program model, structure, commands. Port read mode

Basic version MCS–51 Brief information. Modern 8-bit microcontrollers (MCs) have such real-time control resources, for which previously expensive multi-chip layouts in the form of separate microcomputer boards were used, namely:

● have sufficient memory capacity, its physical and logical division into program memory and data memory(Harvard architecture) and a command system focused on executing control algorithms;

● include all devices (processor, ROM, RAM, input/output ports, interrupt system, means for processing bit information, etc.) necessary to implement a minimal configuration microprocessor control system. In the 70s of the last century the company Intel a family of 8-bit microcontrollers MCS-48, united by a number of common features (bit capacity, command system, set of main functional blocks, etc.), has been developed and launched into industrial production. The basic version of this family includes:

● 8-bit processor;

● internal program memory (1/2/4K bytes);

● internal data memory (64/128/256 bytes);

● up to 27 internal and 16 external I/O lines;

● one 8-bit timer-counter;

● single-level interrupt system with two request sources. In 1980, the same company developed a new family of eight-bit microcontrollers, MCS-51, which is compatible with the architecture of the MCS-48 family, but has greater capabilities.

The architecture of the MCS-51 family turned out to be so successful that it is still one of the standards for 8-bit MKs. Therefore, the object of study was chosen to be microcontrollers of this family, which are widely used in relatively simple control systems.

Various program preparation tools have been developed for the MCS-51 family (compilers, hardware-software emulators, etc.) and there is a large number of libraries of standard routines. The family includes various modifications of microcircuits (chip versions) of microcontrollers. The articles in this section discuss in some detail the basic version of the microcontrollers of the MCS-51 family (the 8051 microcircuit corresponds to the domestic analog KP1816BE51), the simplest in structural and functional terms and from the point of view of understanding.

Subsequent series of microcircuits, while maintaining compatibility with the basic version, differ from it in improved manufacturing technology, electrical parameters, additional hardware and functionality. The following articles are devoted to the structural and functional features of subsequent modifications of the MCS-51 family of microcircuits.
Generalized block diagram of MCS-51. The composition of the MC, a generalized block diagram of which is shown in Fig. 7.1.1 includes:

● 8-bit CPU CPU consisting of ALU, control devices UU and address generator F;

● mask ROM with a capacity of 4K bytes for storing programs;

● RAM with a capacity of 128 bytes for data storage;

● four programmable ports P0–P3 for input– information output;

● block serial interface BPI for exchanging information with external devices via a two-wire line;

● block of BT/C timers/counters to maintain real-time mode;

● BP interrupt block for organizing interruptions of executable programs. These funds form resident part of the microcontroller located directly on the chip. The MK includes a large number of registers, which are assigned to separate functional blocks and are not shown in the diagram.

The diagram also does not show control circuits. Two-way exchange of information between blocks is carried out via internal 8-bit data busШД-8.

By internal 16-bit address busША-16 The address generated in the CPU is output to ROM (12 address bits) and to RAM (8 low-order bits).

When using external memory, the 8 least significant bits of the address are output to port P0 and the 3 or 8 most significant bits to port P2.

To logically expand the interface, combining the functions of port lines is used. As an example in Fig. 7.1.1 the dotted line shows the lines of the P3 port that perform alternative functions of transmitting control signals, the purpose of which will be discussed below. To create an internal clock generator, a quartz resonator and two capacitors are connected to the terminals of the MK microcircuit (Fig. 7.1.1). Instead of an internal clock generator, an external oscillation source can be used for synchronization. Conditional graphic designation MK microcircuits are shown in Fig. 7.1.2, designation and purpose of pins - in table. 7.1.1. Let's consider the functional blocks of the MK and the principle of their operation. Arithmetic logic device. The arithmetic logic device is designed to perform arithmetic (including multiplication and division) and logical operations on eight-bit operands, as well as operations of logical shift, zeroing, setting, etc. The block diagram of the ALU is shown in Fig. 7.1.3.

The ALU includes

● parallel eight-bit adder SM of combinational type with sequential carry, performing arithmetic (addition and subtraction) and logical (addition, multiplication, disparity and identity) operations;

● battery A, providing the functions of the main arithmetic register;

● register B, used to implement multiplication and division operations or as an additional super-operational register, the functions of which are determined by the user;

● registers(software not available) temporary storageРВХ1, РВХ2, intended for receiving and storing operands for the duration of the operation;

● ROM constants ROM, which stores the correction code for the binary decimal representation of data, the mask code for bit operations and the code for constants;

● program status word register PSW, which records the state of the ALU after a completed operation. In table 7.1.2 provides information on the assignment of bits of individual bits of the PSW register. Control device. Control unit (CU) of the central processor intended for coordination collaboration all MK nodes using generated clock pulses and control signals. It consists of (Fig. 7.1.4):

● synchronization and control unit The control system, which generates clock pulses that define machine cycles and their individual states (S) and phases (P), and, depending on the operating mode of the microcontroller, generates the necessary set of control signals. It takes one, two, or four machine cycles to execute a command.

Each machine cycle has six states S1–S6, A each state includes two phases P1, P2, the duration of which is the oscillation period of the clock generator T 0SC.

The duration of the machine cycle is 12T 0SC. All machine cycles are the same, starting with phase S1P1 and ending with phase S6P2.

In addition to the clock pulses, the synchronization device generates two (sometimes one) gating signals for the low byte of the ALE address in each machine cycle in the form of a positive pulse in the phases S1P2–S2P1 and S4P2–S5P1. Timing diagrams in Fig. 7.1.5 illustrate the organization of machine cycles;

● command register RK, command decoder DC and PLM, allowing in each machine cycle to generate a set of micro-operations in accordance with the microprogram of the executed command;

● LVV input/output logic for receiving and issuing signals that ensure the exchange of information from the MK with external devices through ports P0–P3;

● PCON register, which has a single enabled SMOD bit in position PCON.7 to double the serial port data rate. The remaining bits are reserved for later use.
Address generator. Address generator (FA), or PC command counter, intended to form the current 16-bit address of program memory and 8/16-bit address of external data memory. It consists of (Fig. 7.1.6):

● 16-bit buffer B, which communicates between the 8-bit SD data bus and the 16-bit internal bus (IB) of the address former;

● SI increment circuit for increasing the value of the current address program memory per unit;

● register for storing the current address of PTA commands coming from the SI;

● data pointer register DPTR , consisting of two 8-bit registers DPH and DPL. It serves to store a 16-bit address of external data memory and can be used as two independent software-accessible RONs;

● register of the XRF address generator for storing the executive 16-bit address of program memory or 8/16-bit address of external data memory. This register is also used to transmit data through port P0 to external devices when executing the MOVX @Rm, A and MOVX @DPRT, A commands.

Data memory. Data memory intended for receiving, storing and issuing information used during program execution. Internal (resident) data memory (Fig. 7.1.7) consists of RAM with a capacity of 128 bytes, stack pointer S.P. address register RAM RA and decoder Dsh. The stack pointer SP is an 8-bit register designed to receive and store the address of the stack cell that was last accessed. After the reset, the stack pointer is set to address 07H, which corresponds to the beginning of the stack with address 08H. The PA address register together with the Dsh decoder allows access to the required memory cell containing a byte or bit of information.

The MK provides the ability to increase the data memory capacity up to 64 KB by connecting external storage devices. As an example in Fig. 7.1.8 shows the page organization of external VPD data memory with a capacity of 2K bytes using MOVX type commands @ Rm(m = 0; 1). In this case, port P0 operates as a multiplexed address/data bus, three lines of port P2 are used to address a page of external RAM, and the remaining five lines can be used as input/output lines.
In Fig. 7.1.9 shows timing diagrams of read and write cycles when the MK is operating with external RAM. The diagrams indicate:

● RSN - high byte of the PC command counter;

● DPL, DPH - low and high bytes of the DPTR data pointer register, which is used as a register for indirect addressing in the MOVX @DPTR,A and MOVX A,@DPTR commands;

● P2 SFR - P2 port latches;

● Rm (m = 0, 1) - registers used in the MOVX @Rm, A and MOVX A, @Rm instructions as indirect address registers;

● Z - high-resistance state;

● D - the period during which data from port P0 is entered into the microcontroller. Program memory. Program memory is designed to store programs, has its own (separate from data memory) address space and is read-only. It includes a Dsh decoder and ROM (Fig. 7.1.10). A 16-bit PC counter is used to address program memory, so its maximum capacity is 64K bytes. The internal program memory consists of a 4K byte ROM and a 12-bit decoder. External memory is connected according to the diagram in Fig. 7.1.11. If 0 V is supplied to the ¯EA pin of the MK (as shown in Fig. 7.1.11), inner memory programs are disabled. All memory accesses start at address 0000h. When the ¯EA pin is connected to a power source, access to the internal program memory at addresses 0000h–FFFFh and to the external program memory at addresses 0FFFh–FFFFh occurs automatically.

To read the external memory of MK programs, the ¯PSEN signal is generated. When working with internal memory, the read signal is not used. When accessing external program memory, a 16-bit address is always formed. The low byte of the address is transmitted through port P0 in the first half of the machine cycle and is fixed by the cut of the ALE strobe in the register. In the second half of the cycle, port P0 is used to enter a byte of data from external memory into the MK.

The most significant byte of the address is transmitted through port P2 during the entire memory access time.

Timing diagrams of read and write cycles when the MK is operating with external RAM are shown in Fig. 7.1.12.
The diagrams indicate:

● PCL OUT - output of the low byte of the PC program counter;

● RSN OUT - output of the high byte of the PC command counter;

● DPH - high byte of the DPTR data pointer register, which is used as a register for indirect addressing in the MOVX @DPTR,A and MOVX A,@DPTR instructions;

● P2 SFR - P2 port latches;

● INS IN - input of instruction (command) byte from program memory;

● ADDR OUT - issuing the low byte of the external data memory address from the Rm registers (m = 0, 1) or from the DPL register (DPTR low register). I/O ports. Port assignment. Ports P0, P1, P2, P3 intended for exchanging information between the MK and external devices, and also for performing the following functions:

● the low byte of the address A7…A0 is output via port P0; a data byte is output from the MK and entered into the MK when working with external program memory and external data memory (time-separated);

● through port P2, the high byte of the address A15...A8 is output when working with external program memory and external data memory (only when using the MOVX A,@DPTR and MOVX @DPTR,A commands);

● lines of the P3 port can be used to perform alternative functions if 1 is entered in the latch of this line, otherwise 0 is fixed at the line output. Alternative functions of the P3 port pins are given in Table. 7.1.3.

Circuit features of ports

In Fig. 7.1.13 shows diagrams for one channel of each of the MK ports, including:

● a latch for fixing the received data bit;

● output amplifier cascade(driver);

● node connection with output stage (except P2);

● a circuit for transmitting a data bit from the output side of the port, consisting of buffers B2 and B3 (for port P4). The latch is a D-flip-flop, clocked by the internal “Write to latch” signal. The data bit from the direct output of the D flip-flop can be read programmatically through buffer B1 using the “Read Latch” signal to the line of the internal data bus (ID) of the MK.

Output stage port P0 is an inverter, the features of which are manifested in the fact that the load transistor VT2 opens only when accessing external memory (when transmitting addresses and data through the port). In all other modes, the load transistor is closed. Therefore, to use P0 (Fig. 7.1.13, a) as a general-purpose output port, it is necessary to connect external load resistors to its terminals. When writing 1 to the port latch, the inverter transistor VT1 is locked and the external pin of the P0.X port is switched to a high-resistance state. In this mode, the output of port P0.X can serve as an input. If the P0 port is used as a general purpose I/O port, each of its P0.X pins can independently operate as an input or output. Output stages ports P1, P2, P3 (Fig. 7.1.13, b, c, d) made according to inverter circuits with an internal load resistor, which is used as a transistor VT2.

To reduce the switching time when port pins transition from state 0 to state 1, an additional transistor VT3 was introduced in parallel with the load transistor VT2. Transistor VT3, using elements in the gate circuit, is unlocked for a time equal to two oscillation periods of the master quartz oscillator (during phases S1P1, S2P2 of the machine cycle). Output stages ports P0, P2 (Fig. 7.1.13, A, c) using the MX multiplexer can be connected either to latches or to the internal “Address/data” and “Address” buses. The output stage of port P1 (Fig. 7.1.13, 6) is permanently connected to the latch.

If the pin of port P3 is an output and its latch contains 1, then its output stage is controlled by hardware internal signal"Alternative output function" providing the execution of the corresponding alternative function, i.e. one of the signals ¯WR, ¯RD or RxD is generated at the external pin. If the port output is used as an input, then the alternative signal arriving at it (TxD, ¯INT0, ¯INT1, T0, T1) is transmitted to the “Alternative input function” internal line.

Port recording mode.

When a port write command is executed, the new value is written to the latch in phase S6P2 and output directly to the output pin of the port in phase S1P1 of the next machine cycle.

Port read mode

Port read commands read information directly from the external pins of a port or from latch outputs. In the first case, the data bit from the port pin is read programmatically through buffer B2 using the “Read Pins” signal to the line of the internal data bus (SD) of the MK. Note that the signals “Write to latch”, “Read latch”, “Read pins” are generated in hardware when the corresponding commands are executed.

In the second case, the so-called “Read-Modify-Write” mode is implemented, in which the command reads the latch state signal, modifies it if necessary, and then writes it back to the latch. The “Read-Modify-Write” mode is implemented when executing the following commands: ANL, ORL, XRL, JBC; CPL; INC; DEC; DJNC; MOV PX,Y; CLR PX.Y; SETB PX,Y.

Reading information from the outputs of the latches allows you to eliminate errors when interpreting the logical level at the port pin. Read the continuation of the article.

The architecture of the MCS-51 family is largely determined by its purpose - the construction compact And cheap digital devices. All microcomputer functions are implemented using a single microcircuit. The MCS-51 family includes a whole range of microcircuits from the simplest microcontrollers to quite complex ones. Microcontrollers of the MCS-51 family allow you to perform both control tasks for various devices and implement individual components analog circuit. All microcircuits of this family work with the same command system, most of them are carried out in identical cases with matching pinout(numbering of legs for the body). This allows you to use microcircuits from different manufacturers (such as Intel, Dallas, Atmel, Philips, etc.) for the developed device. without rework schematic diagram devices and programs.

Figure 1. Block diagram of the K1830BE751 controller

The block diagram of the controller is presented in Figure 1. and consists of the following main functional units: control unit, arithmetic-logical unit, timer/counter unit, serial interface and interrupt unit, program counter, data memory and program memory. Two-way communication is carried out using an internal 8-bit data bus. Let's take a closer look at the purpose of each block. Almost all members of the MCS-51 family are built according to this scheme. Various microcircuits of this family differ only in special-purpose registers (including the number of ports). Command system all controllers family MCS-51 contains 111 basic commands with a format of 1, 2 or 3 bytes and does not change when moving from one chip to another. This ensures excellent program portability from one chip to another.

Control and synchronization unit

The Timing and Control unit is designed to generate synchronizing and control signals that ensure coordination of the joint operation of the mainframe computer units in all permissible modes of its operation. The control unit includes:

• device for forming time intervals,
• input-output logic,
• command register
• energy management register,
• command decoder, computer control logic.

Device for forming time intervals designed for generating and issuing internal clock signals of phases, clocks and cycles. The number of machine cycles determines the duration of instructions. Almost all computer commands are executed in one or two machine cycles, except for multiplication and division instructions, the execution duration of which is four machine cycles. Let us denote the frequency of the master oscillator by F g. Then the duration of the machine cycle is equal to 12/F g or is 12 periods of the master oscillator signal. I/O logic is designed to receive and output signals that ensure the exchange of information with external devices through the input/output ports P0-P3.

Command register designed to record and store the 8-bit operation code of the command being executed. The operation code, with the help of commands and computer control logic, is converted into microprogram for executing the command.

Demand Control Register (PCON) allows you to stop the microcontroller to reduce power consumption and reduce the level of interference from the microcontroller. An even greater reduction in power consumption and interference can be achieved by stopping the microcontroller master oscillator. This can be achieved by toggling the bits of the PCON consumption control register. For the n-MOS manufacturing option (1816 series or foreign chips that do not have a “c” in the middle of their name), the PCON consumption control register contains only one bit that controls the baud rate of the serial port SMOD, and there are no power consumption control bits.

Together with the article "Architecture of microcontrollers MCS-51" read:

http://site/MCS51/tablms.php

http://site/MCS51/SysInstr.php

http://site/MCS51/port.php

Currently, various companies produce many modifications and analogues of this family, both by Intel and other manufacturers, the clock speed and memory capacity have increased tenfold and continue to increase. The set of modules built into the LSI is also being expanded; a large number of modern models have a built-in resident high-speed ADC with up to 12, and now there may be more, bits. But the MCS51 family is based on Intel LSIs 8051, 80С51, 8751, 87С51, 8031, 80С31, the first samples of which were released in 1980.

Microcontrollers of the MCS51 family are made using high-quality n-MOS technology (series 8ХХХ, analogue - series 1816 in Russia and Belarus) and k-MOS technology (series 8ХСХХ, analogue - series 1830). The second character following 8 means: 0 – there is no EPROM on the chip, 7 – a 4K EPROM with ultraviolet erasure. Third character: 3 – on-chip ROM, 5 – if there is no ROM, then there is a mask ROM on the chip.

And so 80С51 is an LSI based on k-MOS technology with a mask ROM on the chip, 8031 ​​is an n-MOS LSI without program memory (ROM, RPOM) on a chip, 8751 is an n-MOS LSI with a resident (located on the chip) RPOM with ultraviolet erasing. We will further consider the 8751 LSI, making, if necessary, reservations about the differences between other circuits, citing those parameters that were published for the first serial LSIs. If necessary, you can find additional information about all modern modifications in company directories and technical documentation.

A. General characteristics and pin assignments

The MCS51 family is based on five modifications of the MK (having identical basic characteristics), the main difference between which is the implementation of program memory and power consumption (see Table 3.1). The microcontroller is eight-bit, i.e. has commands for processing eight-bit words, has a Harvard architecture, the clock frequency of the basic samples of the family is 12 MHz.

Table 3.1.

Micro circuits	Internal program memory, bytes	Program memory type	Internal data memory, byte	Clock frequency, MHz	Current consumption, mA

MK 8051 and 80C51 contain a mask-programmable ROM program memory with a capacity of 4096 bytes during the manufacture of the chip and are designed for use in mass production. MK 8751 contains a 4096-byte RPOM with ultraviolet erasure and is convenient at the system development stage when debugging programs, as well as during production in small batches or when creating systems that require re-writing during operation.

periodic adjustment.

MK 8031 ​​and 80C31 do not contain built-in program memory. They, like the previously described modifications, can use up to 64 KB of external program memory and are effectively used in systems that require a significantly larger volume (than 4 KB on the chip) of ROM program memory.

Each MK of the family contains a resident data memory with a capacity of 128 bytes with the ability to expand the total amount of RAM data up to 64 KB through the use of external RAM ICs.

eight-bit central processor;

4 KB program memory (8751 and 87C51 only);

128 byte data memory;

four eight-bit programmable I/O ports;

two 16-bit multi-mode timer/counters;

auto-vector interrupt system with five vectors and two software-controlled priority levels;

serial interface, including a universal duplex transceiver capable of operating in four modes;

clock generator.

The MK command system contains 111 basic commands with a format of 1, 2, or 3 bytes. The microcontroller has:

32 general purpose registers RON, organized as four banks of eight registers each with names R0... R7, the choice of one bank or another is determined by the program by setting the corresponding bits in the program status register PSW;

128 software-controlled flags (bit processor, see below);

a set of registers of special functions that control MK elements.

There are the following operating modes of the microcontroller:

1). General reset. 2).Normal functioning. 3).Low power consumption mode and idle mode. 4). Programming mode for resident RPOM, if available.

Here we will focus on the first two operating modes; a detailed description of the composition and operation of the MK in all modes is given in Appendix P1.

The RON and the bit processor area are located in the address space of the resident RAM with addresses from 0 to 80h.

In the upper zone of the addresses of the resident RAM there are special function registers (SFR, Special Function Registers). Their purpose is given in table. 3.2.

Table 3.2.	Designation
	Name
	Battery
	Register B
	Program Status Register
	Stack pointer
	Data pointer.
	2 bytes:
	Low byte
	High byte
	Interrupt Priority Register
	Interrupt enable register
	Timer/Counter Mode Register
	Timer/counter 0. Low byte
	Timer/counter 1. High byte
	Timer/counter 1. Low byte
	Serial Port Control
	Serial Buffer
	Consumption management

* - registers, allowing bitwise addressing

Let's briefly look at the functions of the SFR registers shown in Table 3.2.

Battery ACC - accumulator register. Commands designed to work

you with the battery, use the mnemonic "A", for example, MOV A, P2 . The ACC mnemonic is used, for example, when bitwise addressing an accumulator. Thus, the symbolic name of the fifth bit of the accumulator when using the A5M51 assembler will be as follows: ACC. 5. .

Register IN . Used during multiplication and division operations. For other instructions, register B can be treated as an additional real-time register.

Register state programs P.S.W. contains information about the state of the program and is installed partly automatically based on the result of the operation performed, and partly by the user. The designation and purpose of the register bits are given in Tables 3.3 and 3.4, respectively.

Table 3.3.

Table 3.2.

Table 3.4.

	Designation			Bit assignment		Bit access
				Carry flag.		Changes during the execution of a series of arithmetic and logical instructions.
				Hardware or software		Changes during the execution of a series of arithmetic and logical instructions.
				Additional carry flag.		Set/cleared in hardware during addition or subtraction instructions to indicate a carry or borrow in bit 3 when the least significant nibble of the result (D0-D3) is generated.
						Set/cleared in hardware during addition or subtraction instructions to indicate a carry or borrow in bit 3 when the least significant nibble of the result (D0-D3) is generated.
				Flag 0. User defined flag.		Set/cleared in hardware during addition or subtraction instructions to indicate a carry or borrow in bit 3 when the least significant nibble of the result (D0-D3) is generated.
			Programmatically
				Working Register Bank Index		Changes during the execution of a series of arithmetic and logical instructions.
				Bank 0 with addresses (00Н - 07Н) Bank 1 with addresses (08Н - 0FН) Bank 2 with addresses (10Н - 17Н) Bank 3 with addresses (18Н - 1FН)
				Overflow flag.		Changes during the execution of a series of arithmetic and logical instructions.

Set or cleared by hardware during execution of arithmetic instructions to indicate an overflow condition Spare. Contains a writable and readable trigger that can be used Parity bit. - An 8-bit register whose contents are incremented before writing data to the stack when PUSH and CALL instructions are executed. On initial reset, the stack pointer is set to 07H and the stack area in the data RAM starts at address 08H. If necessary, by overriding the stack pointer, the stack area can be located anywhere in the internal RAM of the microcontroller data.

Set or cleared by hardware during execution of arithmetic instructions to indicate an overflow condition data DPTR consists of a high byte (DPH) and a low byte

(DPL). Contains a 16-bit address when accessing external memory. Can be used

be either a 16-bit register or two independent eight-bit registers.

Port0 - PortZ. Separate bits of the registers of special functions P0, P1, P2, RZ are the “latches” bits of the ports P0, P1, P2, RZ.

Buffer consistent port SBUF represents two separate registers: the transmitter buffer and the receiver buffer. When data is written to the SBUF, it enters the transmitter buffer, and writing a byte to the SBUF automatically initiates transmission through the serial port. When data is read from SBUF, it is fetched from the receiver buffer.

Registers timer. Register pairs (TH0, TL0) and (TH1, TL1) form 16

bit counting registers for timer/counter 0 and timer/counter 1, respectively.

Registers management. Registers of special functions IP, IE, TMOD, TCON, SCON and PCON contain control bits and status bits of the interrupt system, time-

meters/counters and serial port. They will be discussed in detail below.

RxD TxD INT0 INT1 T0 T1 WR

P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

RST BQ2 BQ 1 E.A.

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

When functioning, the MC provides:

the minimum execution time for addition commands is 1 μs;

hardware multiplication and division with a minimum execution time of 4 μs.

The MK provides the ability to set the frequency of the internal oscillator using quartz, an LC chain or an external oscillator.

The extended instruction system provides byte and bit addressing, binary and binary decimal arithmetic, overflow indication and even/odd determination, and the ability to implement a logical processor.

The most important and distinctive feature of the MCS51 family architecture is that the ALU can manipulate single-bit data in addition to performing operations on 8-bit data types.

Individual software-accessible bits can be set, cleared, or replaced by their complement, can be forwarded, checked, and

Fig.3.2.

External pins

microcontroller

used in logical calculations.

Whereas support for simple data types (if available) «0 While the current trend toward longer word lengths may seem like a step backward at first glance, this quality makes the MCS51 family of microcontrollers particularly suitable for controller-based applications. The operating algorithms of the latter presuppose the presence of input and output Boolean variables, which are difficult to implement using standard microprocessors. All these properties are collectively called the Boolean processor of the MCS51 family. While the current trend toward longer word lengths may seem like a step backward at first glance, this quality makes the MCS51 family of microcontrollers particularly suitable for controller-based applications. This powerful ALU makes the MCS51 family of microcontrollers suitable for both real-time control applications and data-intensive algorithms.

The circuit diagram of the microcontroller is shown in Fig. 3.2. In the basic version it is packaged in a 40-pin DIP package. Let's look at the purpose of the pins. Let's start with the power pins IN" And

"5

, through which he receives basic nutrition.

Current consumption is given in table.

3.1.

Conclusion

"RST" - microcontroller reset. When an active high level is applied to this pin, the

mode

general

reset

Table 3.5.

	Information
	Uncertain
	0ХХХ0000V for k-MOS 0XXXXXXXB for n-MOS

The RST pin also has an alternative function.

Backup power is supplied through it to keep the contents of the microcontroller RAM unchanged when the main one is removed. conclusions BQ1, – BQ2

The circuit diagram of the microcontroller is shown in Fig. are intended for connecting a quartz resonator that determines the clock frequency of the MK. (EA` E xternal A – dress external address)

The circuit diagram of the microcontroller is shown in Fig. - designed to activate the mode of reading control codes from external program memory when an active low level is applied to this pin. (The output has an alternative purpose (function). It is supplied with programming voltage from the RPOM in programming mode. PME P EA` rogram – M emory nable permission

The circuit diagram of the microcontroller is shown in Fig. memory (xternal A programs ) - is designed to control the cycle of reading from program memory and is automatically activated by the MK in each machine cycle. EA` rogram – M ALE L ength

junior

addresses)

strobes the output of the low-order part of the address via port P0.

The output is also used when programming the RPOM, while a strobe pulse for the programming process is supplied to it.

The MK contains four groups of ports: P0, P1, P2, and P3.

These are the remaining 40 pins of the microcontroller.

These ports can serve for bit-by-bit input and output of information, but in addition, each of them has its own specialization.

A generalized functional diagram of the port is shown in Fig.

unit. When the “read latch” line is activated, the output of the “AND” cell to which this line is connected appears.

her tires MK D Q

Write to latch C Q

Read latch

Port pin

The latch state is transmitted to the internal bus of the MC when activated

“read output” - the state of the external pin of the port.

Port P0 – universal bidirectional port

I/O

Beyond this port

the function of organizing external address buses and

Rice. 3.3.

Functional diagram of the microcontroller port

Port data for expanding program memory and data memory microcontroller.

Port P2 When the external program memory is accessed or a command is executed to access the external data memory, the low-order part of the address (A0...A7) is set at the port pins, which is gated high at the ALE pin.

Port Then, when writing data to memory, the recorded information from the internal bus of the MK is sent to the pins of the P0 port. In read operations, on the contrary, information from the port pins is sent to the internal bus.

A feature of the P0 port is the absence of a “pull-up” transistor N2, which provides power to the output. – When writing to the unit port latch, it is simply transferred to a high-impedance state, which is necessary for normal operation of the data bus. (If it is necessary to power any external devices through the output, external resistors should be provided from the power circuits to the port output. P1 – universal bidirectional I/O port without alternative functions.– a universal bidirectional I/O port, which, as an alternative function, issues the high part of the address (A8...A15) when accessing external memory. P3– a universal bidirectional I/O port, each bit of which provides for the implementation of various alternative functions.

In this case, alternative functions are implemented only if ones are written to the latches of the port pins; otherwise, the execution of alternative functions is blocked. – Let us list them separately for each bit: (P3.0 RxD – universal bidirectional I/O port without alternative functions.– a universal bidirectional I/O port, which, as an alternative function, issues the high part of the address (A8...A15) when accessing external memory. P3 R

ead e – X (internal errupt, interrupt) – external interrupt input 0.

P3.3 – INT1` – external interrupt input 1.

P3.4 – С/T0 – zero built-in timer/counter input.

P3.5 – C/T1 – input of the first built-in timer/counter.

P3.6 – WR` (W rite, write) – output for controlling the write cycle in the data memory.

P3.7 – RD` (If it is necessary to power any external devices through the output, external resistors should be provided from the power circuits to the port output. ead, read) – control output of the read cycle from data memory.

The pins of port P1, P2 and P3 are capable of outputting a current of about 0.2 mA per unit and receiving a current of 3 mA at zero; the pins of port P0 are more powerful and are capable of delivering a current of about 0.8 mA in one unit and receiving a current of 5 mA at zero. Brief information about the purpose of the microcontroller pins is given in Table 3.6.

Table 3.6.

	Table 3.2.	Output purpose
		8-bit bidirectional port P1.	Address input A0-A7 when checking internal ROM (RPM)
		enter exit
		General reset signal.	Address input A0-A7 when checking internal ROM (RPM)
		RAM backup power output from an external source (for 1816)
		8-bit bidirectional P3 port with additional features
		Receiver Serial Data - RxD
		Transmitter serial data - TxD
		External interrupt input 0-INT0`
		External interrupt input 1-INT1`
		Timer/counter input 0: - T0
		Timer/counter input 1: - T1
		Strobe signal output when writing to external data memory: - WR`	Strobe signal output when reading from external data memory – RD`
		Leads for connecting a quartz resonator.
		exit input	Address input A0-A7 when checking internal ROM (RPM)
		General conclusion
		8-bit bidirectional port P2.	Address input A0-A7 when checking internal ROM (RPM)
		Address A8-A15 output in external memory mode.	Address input A0-A7 when checking internal ROM (RPM)
		In the internal ROM check mode, pins P2.0 - P2.6 are used as the input of addresses A8-A14.	Address input A0-A7 when checking internal ROM (RPM)
		Pin P2.7 - ROM reading permission.

Program Memory Resolution

Address fixation enable output signal.

When programming the RPOM signal: PROG

Blocking work with internal memory.

When programming the RPOM, the UPR signal is given

8-bit bidirectional port P0.

Address/data bus for working with external memory.

Data output D7-D0 in internal ROM (RPM) test mode. Power output from +5V voltage source supports a single set of instructions, which is designed to execute 8-bit actuator control algorithms. It is possible to use fast methods for addressing internal RAM and performing bit operations on small data structures. There is an extensive system for addressing single-bit variables as an independent data type, which allows the use of individual bits in logical and control commands of Boolean algebra.

Addressing modes : command set Power output from +5V voltage source supports the following addressing modes. Direct addressing: The operand is determined by the 8-bit address in the instruction. Direct addressing is used only for the lower half of the internal data memory and registers SFR. Indirect addressing: The instruction addresses a register containing the address of the operand. This type addressing is used for external and internal RAM. Registers can be used to specify 8-bit addresses R0 And R1 selected register bank or stack pointer SP. For 16-bit addressing, only the data pointer register is used DPTR.

Register instructions : registers R0–R7 current register bank can be addressed via specific instructions containing a 3-bit field indicating the register number in the instruction itself. In this case, the corresponding address field is missing in the command. Operations using special registers: some instructions use individual registers (for example, accumulator operations, DPTR, etc.). In this case, the operand address is not specified in the command at all. It is predetermined by the operation code.

Immediate constants : the constant can be located directly in the command after the opcode.

Index addressing : Index addressing can only be used to access program memory and only in read mode. In this mode, tables in program memory are viewed. 16-bit register ( DPTR or program counter) indicates the base address of the desired table, and the accumulator indicates the entry point into it.

Command sethas 42 command mnemonics to specify the 33 functions of this system. The syntax of most assembly language instructions consists of a function mnemonic followed by operands indicating addressing methods and data types. Various types data or addressing modes are determined by the set operands, not by changes in mnemonics.

The command system can be divided into five groups: arithmetic instructions; logical commands; data transfer commands; bit processor commands; branching and control transfer commands. The notations and symbols used in the command system are given below.

Table. Notations and symbols used in the command system

Designation, symbol	Purpose
	Name
	Registers of the currently selected register bank
	The number of the loaded register specified in the command
direct	Directly addressable 8-bit internal data cell address, which can be an internal data RAM cell (0–127) or an SFR special function register (128–255)
	Indirectly addressable 8-bit internal data RAM cell
	8-bit direct data included in the operation code (OPC)
dataH	Most significant bits (15–8) of the immediate 16-bit data
dataL	Least significant bits (7–0) of immediate 16-bit data
	11-bit destination address
addrL	Least significant bits of destination address
	8-bit signed offset byte
	Directly addressable bit whose address contains the COP located in the internal data RAM or special function register SFR
a15, a14...a0	Destination address bits
	Contents of element X
	Contents at the address stored in element X
	Bit M of element X
+ – * AND OR XOR /X	Operations: addition subtraction multiplication divisions logical multiplication (AND operation) logical addition (OR operation) addition modulo 2 (exclusive OR) inversion of element X

Function mnemonics are uniquely associated with specific combinations of addressing methods and data types. In total, there are 111 such combinations possible in the command system.

2. Arithmetic and logical instructions

How p example arithmetic instruction, the addition operation can be performed by one of the following commands.

ADDA,7 F 16 – add the number 7 to the contents of register A F 16 and store the result in register A;

ADDA,@ R0 – add to the contents of register A the number whose address (@ – commercial at ) is stored in a register If it is necessary to power any external devices through the output, external resistors should be provided from the power circuits to the port output. 0 (indirect addressing), and store the result in register A;

ADD A,R7– add the contents of register A to the contents of register If it is necessary to power any external devices through the output, external resistors should be provided from the power circuits to the port output. 7 and save the result in register A;

ADD A,#127– add to the contents of register A a number whose storage cell address is 127 ( # – number symbol), and save the result in the registry T- re A.

All arithmetic instructions are executed in one machine cycle with the exception of the instruction INC DPTR(data pointer offset DPTR to the next byte), requiring two machine cycles, as well as multiplication and division operations performed in 4 machine cycles. Any byte in the internal data memory can be incremented and decremented without using a battery.

Instructions MUL AB performs multiplication (multiplication) of the data in the accumulator by the data in register B, placing the product in registers A (low half) and B (high half).

Instructions DIV AB divides (division) the contents of the accumulator by the value in register B, leaving the remainder in B and the quotient in the accumulator.

Instructions DA A is intended for binary decimal arithmetic operations (arithmetic operations on numbers represented in binary decimal code). It does not convert binary number to BCD, but only provides the correct result when adding two binary decimal numbers.

Example logical command: A logical AND operation can be performed by one of the following commands:

ANLA,7 F 16 – logical multiplication of the contents of register A by the number 7 F 16 and the result is stored in register A;

ANLA,@ R1 – logical multiplication of the contents of register A by the number whose address is stored in the register If it is necessary to power any external devices through the output, external resistors should be provided from the power circuits to the port output. 1 (indirect addressing), and store the result in register A;

ANL A,R6– logical multiplication of the contents of register A by the contents of the register If it is necessary to power any external devices through the output, external resistors should be provided from the power circuits to the port output. 6, and save the result in register A;

ANL A,#53 – logical multiplication of the contents of register A by a number whose storage cell address is 53 16, and the result is stored in register A.

All logical operations on the contents of the accumulator are performed in one machine cycle, the rest - in two. Logical operations can be performed on any of the lower 128 bytes of internal data memory or on any register SFR (special function registers) in direct addressing mode without using a battery.

The rotary shift operations RL A, RLC A, etc. move the contents of the accumulator one bit to the right or left. In the case of a left cyclic shift, the least significant bit is moved to the most significant position. In the case of a right cyclic shift, the opposite occurs.

Operation SWAP A exchanges the low and high tetrads in the battery.

3. Data transfer commands

Team MOV dest,src allows you to transfer data between internal RAM cells or special function register areas SFR without using a battery. In this case, work with the upper half of the internal RAM can only be carried out in indirect addressing mode, and access to registers SFR– only in direct addressing mode.

In all microcircuits Power output from +5V voltage source The stack is placed directly in the data resident memory and grows upward. Instructions PUSH first increments the value in the stack pointer register SP, and then writes a byte of data onto the stack. Teams PUSH And POP are used only in direct addressing mode (writing or restoring a byte), but the stack is always accessible when indirectly addressing via a register SP. Thus, the stack can also use the top 128 bytes of data memory. The same considerations exclude the possibility of using stack instructions to address registers SFR.

Data transfer instructions include a 16-bit transfer operation MOV DPTR,#data16, which is used to initialize the data pointer register DPTR when viewing tables in program memory or to access external data memory.

Operation XCH A,byte used to exchange data between the accumulator and the addressed byte. Team XCHD A,@Ri similar to the previous one, but is performed only for the lower tetrads involved in the exchange of operands.

To access external data memory, only indirect addressing is used. In the case of single-byte addresses, registers are used R0 or R1 current register bank, and for 16-bit – data pointer register DPTR. With any method of accessing external data memory, the battery plays the role of a source or receiver of information.

To access tables located in program memory, use the following commands:

MOVC A,@A+ DPTR ;

MOVC A,@A+ PC .

The contents of the data pointer register are used as the base address of the table DPTR or PC(program counter), and the offset is taken from xternal. These instructions are used exclusively to read data from program memory, but not to write to it.

4. Boolean operations

Microcircuits Power output from +5V voltage source contain a “Boolean” processor. The internal RAM has 128 directly addressable bits. Special function register space SFR can also support up to 128 bit fields. Bit instructions perform conditional branches, transfers, resets, inversions, AND and OR operations. All specified bits are available in direct addressing mode.

Carry bit CF in the special function register “program status word” P.S.W." is used as a one-bit accumulator for a Boolean processor.

5. Jump instructions

The addresses of jump operations are indicated in assembly language by a label or a real value in program memory space. Conditional branch addresses are assembled into a relative offset - a sign byte added to the program counter PC if the transition condition is met. The boundaries of such transitions lie between minus 128 and 127 relative to the first byte following the instruction. In the special function register "program status word" P.S.W." there is no zero flag, so the instructions JZ And JNZ check the condition “equal to zero” as testing the data in the accumulator.

There are three types of unconditional jump command: SJMP, LJMP And AJMP– destination addresses that differ in format. Instructions SJMP encodes the address as a relative offset, and takes two bytes. The jump distance is limited to the range from minus 128 to 127 bytes relative to the instruction following SJMP.

In the instructions LJMP The destination address is used as a 16-bit constant. The command length is three bytes. The destination address can be located anywhere in program memory.

Team AJMP uses an 11-bit address constant. The command consists of two bytes. When this instruction is executed, the lower 11 bits of the address counter are replaced by the 11-bit address from the instruction. The five most significant bits of the program counter PC remain unchanged. Thus, the transition can be made within a 2K-byte block in which the instruction following the instruction is located AJMP.

There are two types of command calls to a subroutine: LCALL And ACALL. Instructions LCALL uses the 16-bit address of the called subroutine. In this case, the subroutine can be located anywhere in the program memory. Instructions ACALL uses an 11-bit subroutine address. In this case, the called routine must be located in a single 2K byte block with the instruction following ACALL. Both versions of the instruction push the address of the next instruction onto the stack and load it into the program counter PC corresponding new value.

The subroutine ends with the instruction RET, which allows you to return to the instruction following the command CALL. This instruction pops the return address off the stack and loads it into the program counter. PC . Instructions RETI used to return from interrupt routines. The only difference RETI from RET is that RETI informs the system that interrupt processing has completed. If at the time of execution RETI there are no other interrupts, then it is identical RET.

Instructions DJNZ designed to control cycles. To execute a loop N once you need to load a byte with a value into the counter N and close the loop body with the command DJNZ, indicating the beginning of the cycle.

Team CJNE compares its two operands as unsigned integers and jumps to the address specified therein if the operands being compared are not equal. If the first operand is less than the second, then the carry bit CF is set to "1".

All instructions in assembled form occupy 1, 2 or 3 bytes.

ARCHITECTURE OF MICROCONTROLLER FAMILYMCS-51

Lecture notes for courses

“Microprocessors in control systems”, “Microprocessor technology”

"Microprocessor tools and systems"

for students of all forms of study specialties

072000 – Standardization and certification

210200 – Automation of technological processes

230104 – Computer-aided design systems

Tambov 2005

INTRODUCTION.. 3

1. STRUCTURE OF THE INTEL 8051 MICROCONTROLLER. 3

1.1. Organization of memory. 5

1.2. Arithmetic-logical device. 6

1.3. Resident memory for programs and data. 7

1.4. Accumulator and general purpose registers. 8

1.5. The program status word register and its flags. 9

1.6. Pointer registers. 10

1.7. Special function registers. eleven

1.8. Control and synchronization device. eleven

1.9. Parallel information input/output ports. 12

1.10. Timers/counters. 13

1.11. Serial port. 18

1.11.1. Register SBUF.. 18

1.11.2. Serial port operating modes. 18

1.11.3. Register SCON.. 19

1.11.4. Reception/transmission speed. 21

1.12. Interrupt system. 22

2. COMMAND SYSTEM OF THE INTEL 8051 MICROCONTROLLER. 26

2.1. General information. 26

2.1.1. Types of commands. 27

2.1.2. Operand types. 28

2.1.3. Methods of addressing data. thirty

2.1.4. Result flags. 31

2.1.5. Symbolic addressing. 32

2.2. Data transfer commands. 33

2.2.1. Structure of information links. 33

2.2.2. Accessing the battery. 33

2.2.3. Accessing external data memory. 34

2.2.4. Accessing program memory... 34

2.2.5. Access to the stack. 35

2.3. Arithmetic operations. 35

2.4. Logical operations. 39

2.5. Control transfer commands. 43

2.5.1. Long transition. 43

2.5.2. Absolute transition. 43

2.5.3. Relative transition. 44

2.5.4. Indirect transfer. 44

2.5.5. Conditional jumps.. 44

2.5.6. Subroutines.. 47

2.6. Operations with bits. 48

Test questions... 49

LITERATURE.. 50

Appendix COMMAND SYSTEM INTEL 8051. 51

INTRODUCTION

Since the 80s of the 20th century, an independent class has emerged in microprocessor technology integrated circuits– single-chip microcontrollers that are designed for integration into devices for various purposes. They are distinguished from the class of single-chip microprocessors by the presence of internal memory and developed means of interaction with external devices.

8-bit single-chip microcontrollers of the MCS-51 family are widely used. This family was formed on the basis of the Intel 8051 microcontroller, which has gained great popularity among developers of microprocessor control systems due to its well-designed architecture. The microcontroller architecture is a set of internal and external software-accessible hardware resources and command systems.

Subsequently, Intel released about 50 models based on the operating core of the Intel 8051 microcontroller. At the same time, many other companies, such as Atmel, Philips, began production of their microcontrollers developed in the MCS-51 standard. There is also domestic analogue Intel 8051 microcontroller - K1816BE51 chip.

2. STRUCTURE OF THE INTEL 8051 MICROCONTROLLER

The Intel 8051 microcontroller is based on high-level n-MOS technology. Its main characteristics are as follows:

· eight-bit central processor optimized for implementation of control functions;

· built-in clock generator (maximum frequency 12 MHz);

· program memory address space - 64 KB;

· data memory address space - 64 KB;

· internal program memory - 4 KB;

· internal data memory - 128 bytes;

· additional capabilities for performing Boolean algebra operations (bitwise operations);

· 2 sixteen-bit multifunctional timers/counters;

· full-duplex asynchronous transceiver (serial port);

· vectored interrupt system with two priority levels and five event sources.

Figure 1 - Block diagram of the Intel 8051 microcontroller

The basis of the block diagram (Fig. 1) is formed by an internal bidirectional 8-bit bus, which interconnects the main nodes and devices of the microcontroller: resident program memory (RPM), resident data memory (RDM), arithmetic-logical unit (ALU), register unit special functions, control unit (CU), parallel I/O ports (P0-P3), as well as programmable timers and a serial port.

2.1. Memory organization

This microcontroller has built-in (resident) and external program and data memory. The resident program memory (RPM) has a capacity of 4 KB, and the resident data memory (RDM) has a capacity of 128 Bytes.

Depending on the modification of the microcontroller, RPM is implemented in the form of a mask ROM, one-time programmable or reprogrammable ROM.

If necessary, the user can expand the program memory by installing an external ROM. Access to internal or external ROM is determined by the value of the signal at pin EA (External Access):

EA=VCC (supply voltage) - access to internal ROM;

EA=VSS (ground potential) - access to external ROM.

External program and data memory can be 64 KB each and can be addressed using ports P0 and P2. Figure 2 shows the Intel 8051 memory card.

Figure 2 - Intel 8051 memory organization

External ROM read strobe - (Program Store Enable) is generated when accessing external program memory and is inactive while accessing the ROM located on the chip.

The area of ​​lower program memory addresses (Fig. 3) is used by the interrupt system. The INTEL 8051 chip architecture provides support for five interrupt sources. The addresses to which interrupt control is transferred are called interrupt vectors.

Figure 3 - Map of the lower program memory area

2.2. Arithmetic logic unit

The 8-bit arithmetic logic unit (ALU) can perform the arithmetic operations of addition, subtraction, multiplication, and division; logical operations AND, OR, exclusive OR, as well as operations of cyclic shift, reset, inversion, etc. Software-inaccessible registers T1 and T2, intended for temporary storage of operands, a decimal correction circuit (DCU) and a feature generation circuit are connected to the inputs operation result (PSW).

The simple addition operation is used in the ALU to increment the contents of registers, advance the data pointer register (RAR), and automatically calculate the next program resident memory address. The simplest subtraction operation is used in the ALU to decrement registers and compare variables.

The simplest operations automatically form “tandems” to perform operations such as, for example, incrementing 16-bit register pairs. The ALU implements a mechanism for cascading execution of simple operations to implement complex commands. So, for example, when executing one of the conditional control transfer commands, based on the comparison result in the ALU, the program counter (PC) is incremented three times, the RDM is read twice, an arithmetic comparison of two variables is performed, a 16-bit transition address is formed, and a decision is made on whether to or not make the transition according to the program. All of the above operations are performed in just 2 μs.

An important feature of the ALU is its ability to operate not only bytes, but also bits. Individual software-accessible bits can be set, cleared, inverted, transmitted, tested, and used in logical operations. This ability is quite important, since to control objects, algorithms are often used that contain operations on input and output Boolean variables, the implementation of which is associated with certain difficulties using conventional microprocessors.

Thus, the ALU can operate with four types of information objects: Boolean (1 bit), digital (4 bits), byte (8 bits) and address (16 bits). The ALU performs 51 different operations to forward or transform this data. Since there are 11 addressing modes (7 for data and 4 for addresses), by combining the operation and addressing mode, the basic number of 111 instructions is expanded to 255 out of 256 possible with a single-byte opcode.

2.3. Resident program and data memory

Residential (on-chip) program memory (RPM) and data memory (RDM) are physically and logically separated, have different addressing mechanisms, operate under the control of different signals, and perform different functions.

The RPM program memory has a capacity of 4 KB and is designed to store commands, constants, initialization control words, conversion tables for input and output variables, etc. The memory has a 16-bit address bus, through which access is provided from the PC program counter or from the register. data pointer (DPTR). DPTR functions as a base register for indirect program jumps or is used in table operations.

The RDM data memory is designed to store variables during execution of an application program, is addressable by one byte and has a capacity
128 bytes. In addition, its address space is adjacent to the addresses of special function registers, which are listed in Table. 1.

The program memory, like the data memory, can be expanded to
64 KB by connecting external chips.

Table 1

Special Function Register Block

	Designation
		Name
		Accumulator expander register
		Program status word
		Stack pointer register
		Data pointer register
		Interrupt Priority Register
		Interrupt Mask Register
		Timer/Counter Mode Register
		Timer Control/Status Register
		Timer 0 (high byte)
		Timer 0 (low byte)
		Timer 1 (high byte)
		Timer 1 (low byte)
		Transceiver Control Register
		Transceiver Buffer
		Power control register

Note. Registers whose names are marked with (*) allow individual bits to be addressed.

2.4. Accumulator and general registers

The accumulator (A) is the source of the operand and the location of the result when performing arithmetic, logical operations and a number of data transfer operations. In addition, shift operations, checking for zero, generating a parity flag, etc. can only be performed using the accumulator.

The user has four banks of 8 general purpose registers R0–R7 at his disposal (Fig. 9). However, it is possible to use the registers of only one of the four banks, which is selected using the PSW register bit.

2.5. Program status word register and its flags

When many instructions are executed in the ALU, a number of operation attributes (flags) are generated, which are recorded in the program status word (PSW) register. In table 2 provides a list of PSW flags, gives their symbolic names and describes the conditions for their formation.

table 2

PSW Program Status Word Format

		Name and purpose
		Carry flag. Set and reset by hardware or software when performing arithmetic and logical operations
		Auxiliary carry flag. Set and cleared only by hardware when adding and subtracting instructions are executed and signals a carry or borrow in bit 3
		Flag 0. Can be set, cleared, or checked by the program as a user-specified flag.
		Selecting a register bank. Set and reset by software to select a working bank of registers (Table 3)
		Overflow flag. Set and reset by hardware when performing arithmetic operations
		Not used
		Parity flag. Set and reset by hardware in each cycle and fixes the odd/even number of one bits in the accumulator, i.e. performs parity

Table 3

Selecting a working register bank

			Address Boundaries

The most “active” PSW flag is the carry flag, which is involved and modified during many operations, including addition, subtraction and shifts. In addition, the carry flag (CY) functions as a “Boolean accumulator” in bit-manipulating instructions. The overflow flag (OV) detects arithmetic overflow in signed integer operations and makes it possible to use arithmetic in two's complement codes. The ALU does not control the register bank selection flags (RS0, RS1), their value is completely determined by the application program and is used to select one of the four register banks.

As a byte, the PSW register can be represented as follows:

In microprocessors whose architecture relies on an accumulator, most instructions operate on the accumulator using implicit addressing. The Intel 8051 is different. Although the processor is based on a battery, it can execute many commands without its participation. For example, data can be transferred from any RDM cell to any register, any register can be loaded with an immediate operand, etc. Many logical operations can be performed without involving an accumulator. Additionally, variables can be incremented, decremented, and checked without using an accumulator. Flags and control bits can be checked and changed in the same way.

2.6. Pointer registers

The 8-bit stack pointer (SP) can address any RDM area. Its contents are incremented before the data is stored on the stack during PUSH and CALL instructions. The contents of the SP are decremented after the POP and RET commands are executed. This method of addressing stack elements is called pre-increment/post-decrement. During the initialization of the microcontroller, after the RST signal, code 07H is automatically loaded into the SP. This means that unless the application program overrides the stack, the first data element on the stack will be located in RDM location 08H.

The two-byte data pointer register DPTR is typically used to capture a 16-bit address in external memory access operations. By microcontroller commands, the data pointer register can be used either as a 16-bit register or as two independent 8-bit registers (DPH and DPL).

2.7. Special function registers

The registers, symbolically named IP, IE, TMOD, TCON, SCON, and PCON, are used to latch and programmatically change the control and status bits of the interrupt circuitry, timer/counter, serial transceiver, and power management. Their organization will be described in detail in sections 1.8-1.12, when considering the features of the microcontroller in various modes.

2.8. Control and synchronization device

A quartz resonator connected to the external pins of the microcontroller controls the operation of the internal oscillator, which in turn generates synchronization signals. The control unit (CU), based on synchronization signals, generates a machine cycle of a fixed duration equal to 12 generator periods. Most microcontroller instructions are executed in one machine cycle. Some instructions that operate on 2-byte words or access external memory take two machine cycles to complete. Only the division and multiplication instructions require four machine cycles. Based on these operating features of the control device, the execution time of application programs is calculated.

In the microcontroller circuit, an instruction register (IR) is adjacent to the control device. Its function is to store the code of the command being executed.

Input and output signals of the control and synchronization device:

1. PSEN – program memory resolution,

2. ALE – address fixation enable output signal,

3. PROG – programming signal,

4. EA – blocking work with internal memory,

5. VPP – programming voltage,

6. RST – general reset signal,

7. VPD – memory backup power output from external source,

8. XTAL – connection inputs quartz resonator.

2.9. Parallel input/output ports

All four ports (P0-P3) are designed to input or output information byte by byte. Each port contains a controlled latch register, an input buffer and an output driver.

The output drivers of ports P0 and P2, as well as the input buffer of port P0, are used when accessing external memory. In this case, through port P0 in time multiplexing mode, the low byte of the address is first output, and then the data byte is issued or received. Port P2 outputs the most significant byte of the address in cases where the address width is 16 bits.

All pins of port P3 can be used to implement the alternative functions listed in table. 4. These functions can be enabled by writing 1 to the corresponding bits of the latch register (P3.0-P3.7) of port P3.

Table 4

Alternative P3 Port Functions

		Name and purpose
		Reading. An active low-level signal is generated by hardware when accessing external data memory
		Record. An active low-level signal is generated by hardware when accessing external data memory
		Timer/counter input 1 or test input
		Timer/counter input 0 or test input
		Interrupt request input 1. Senses low level or cutoff signal
		Interrupt request input 0. Senses low level or cutoff signal
		Serial port transmitter output in UART mode. Clock output in shift register mode
		Serial port receiver input in UART mode. Data input/output in shift register mode

Port 0 is bidirectional and ports 1-3 are quasi-bidirectional. Each port line can be used independently for input or output.

Based on the RST signal, units are automatically written to the latching registers of all ports, thereby setting them up for input mode.

All ports can be used to organize information input/output via bidirectional transmission lines. However, ports P0 and P2 cannot be used for this purpose if the system has external memory, communication with which is organized through a common shared address/data bus operating in time multiplexing mode.

Accessing I/O ports is possible using commands that operate on a byte, an individual bit, or an arbitrary combination of bits. Moreover, in cases where the port is both an operand and the destination of the result, the control device automatically implements a special mode called “read-modify-write”. This access mode involves inputting signals not from the external pins of the port, but from its latch register, which eliminates incorrect reading of previously output information. This mechanism for accessing ports is implemented in the commands: